CY7C1061GN30-10ZSXI

CY7C1061GN30-10ZSXI is a high-performance CMOS Static RAM organized as 1,048,576 words by 16 bits. To write to the device, take Chip Enables (active-low CE1 LOW and active-low CE2 HIGH) and Write Enable (active-low WE) input LOW. If Byte Low Enable (active-low BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (active-low BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (active-low CE1 LOW and active-low CE2 HIGH) and Output Enable (active-low OE) LOW while forcing the Write Enable (active-low WE) HIGH. If Byte Low Enable (active-low BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (active-low BHE) is LOW, then data from memory appears on I/O8 to I/O15.

• Fast asynchronous SRAM family, 16Mbit density, 16bits data width
• 65nm technology, 2.2V to 3.6V voltage, 10ns speed, dual chip enable
• 1.0V data retention, automatic power down when deselected
• TTL compatible inputs and outputs
• Easy memory expansion with active-low CE1 and CE2 features
• Input leakage current is +1µA maximum at (GND < VI < VCC)
• VCC operating supply current is 90mA typical at (VCC = max, IOUT = 0mA, f = 100MHz)
• Input capacitance is 10pF maximum at (TA = 25°C, f = 1MHz, VCC = 3.3V)
• 40mA typ automatic CE power down current TTL inputs at (max VCC, CE1 > VIH, CE2 < VIL)
• Industrial ambient temperature range from -40°C to +85°C, 54-pin TSOP package