S25FL064LABNFI043

S25FL064LABNFI043 is a FL-L flash memory. The FL-L family connects to a host system via a serial peripheral interface (SPI). In addition, there are double data rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock. The architecture features a page programming buffer that allows up to 256bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block sector, 64KB block sector, or entire chip erase. By using FL-L family devices at the higher clock rates supported, with quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories, while reducing signal count dramatically.

• 64Mb density, floating gate process technology, USON 4 x 4mm / WSON 5 x 6mm package type
• Industrial temperature range from -40 to 85°C
• Clock polarity and phase modes 0 and 3, modes burst wrap, continuous (XIP), QPI
• Commands normal, fast, dual I/O, quad I/O, dualO, quadO, DDR quad I/O
• Serial flash discoverable parameters (SFDP) for configuration information
• Program architecture, 256bytes page programming buffer, program suspend and resume
• Erase architecture, uniform 4KB sector erase, uniform 32KB half block erase
• Uniform 64KB block erase, chip erase, erase suspend and resume
• 100000 program-erase cycles, minimum, 20 year data retention, minimum
• Four security regions of 256-bytes each outside the main flash array